The present invention relates to a clock signal generation apparatus for use in discrete-time analog circuits, etc., such as an A/D converter.
In recent years, as data transfer speed becomes higher due to broadbandization in communication system, a discrete-time (hereafter simply referred to as DT) analog circuit typified by a delta-sigma A/D converter is requested to operate at higher speed. Because of this request for higher speed, the operation timing of a clock signal has become very severe. FIG. 11A shows an example of a switched-capacitor (hereafter simply referred to as SC) integrator serving as a typical circuit component for use in a DT delta-sigma A/D converter and the like. This SC integrator contains a switch (hereafter simply referred to as SW) 41a that is turned ON/OFF by a control signal having clock timing Φ1; a switch 41b that is turned ON/OFF by a control signal having clock timing Φ2; capacitors 42a and 42b; and an operational amplifier 40.
FIG. 11B shows the clock timings Φ1 and Φ2. The SW 41a becomes ON in a zone in which the clock timing Φ1 has H level, and the signal input to the input terminal 43a of the integrator charges the capacitor 42a. At this time, the SW 41b is OFF. Next, when the clock timing Φ1 becomes L level, the SW 41a is turned OFF, and the charging of the capacitor 42a is completed.
Next, the SW 41b becomes ON in a zone in which the clock timing Φ2 has H level, and the charge stored in the capacitor 42a is transferred to the capacitor 42b. As a result, a signal obtained by integrating the input signal is output from the output terminal 43b of the integrator. However, if the clock timing Φ2 becomes H level before the clock timing Φ1 becomes L level at this time, the input signal input to the input terminal 43a of the integrator charges not only the capacitor 42a that is intended to be charged by the input signal but also the capacitor 42b simultaneously. If the H level of the clock timing Φ1 overlaps with the H level of the clock timing Φ2 as described above, the SC integrator does not operate properly as an integrator. Hence, it is necessary to use non-overlap clock signals having a non-overlap time in which the clock timings Φ1 and Φ2 become L level simultaneously as shown in FIG. 11B so that the clock timings Φ1 and Φ2 do not become H level simultaneously.
Generally speaking, since the timing of the above-mentioned non-overlap time is generated using a delay element or the like, the timing varies significantly due to the effect of power supply voltage fluctuations and temperature fluctuations. In some cases, the non-overlap zone may be lost, or the non-overlap zone may become too long and the H-level zones of the clock timings Φ1 and Φ2 may become short. In the case that the non-overlap zone is lost, there occurs a problem that the SC integrator malfunctions as described above. Furthermore, in the case that the H-level zones of the clock timings Φ1 and Φ2 become short, since the charging of the capacitor 42a using the input signal is performed in the H-level zone of the clock timing Φ1 and the integration is performed in the H-level zone of the clock timing Φ2, the circuit components including the operational amplifier 40 are required to be operated at higher speed because the H-level zones are short. Hence, the conventional SC integrator has a problem of causing increase in the power consumption and the area of the circuit. Consequently, in a DT analog circuit, such as the SC delta-sigma A/D converter, it is important to generate optimal non-overlap clock signals, i.e., clock signals in which a non-overlap time is obtained securely and the H-level zones of the clock timings are as long as possible.
FIG. 12 is a block diagram showing the configuration of a non-overlap clock signal generator serving as a conventional clock signal generation apparatus disclosed in Japanese Patent Application Laid-open Publication No. 2002-108492.
Next, this conventional non-overlap clock signal generator will be described briefly below referring to the block diagram of FIG. 12.
The two-phase clock signal generation apparatus 101 shown in FIG. 12 contains a machine clock signal output section 102; a control circuit section 103 composed of a CPU; a storage circuit section 105 in which adjustment data for adjusting the non-overlap time of two-phase clock signals is stored; and a two-phase clock signal generation section 104 for generating the two-phase clock signals.
The control circuit section 103 reads appropriate data from the storage circuit section 105 in which adjustment data for adjusting the non-overlap time of the two-phase clock signals is stored and then outputs setting data to the two-phase clock signal generation section 104, depending on the sensor signals output from the temperature sensor 106 and the voltage sensor 107 for detecting operation environment. The two-phase clock signal generation section 104 is configured so that the overlap time between the A-phase clock signal and the B-phase clock signal thereof can be set variably on the basis of the setting data supplied from the control circuit section 103. In the two-phase clock signal generation apparatus 101 configured as described above, the non-overlap time is adjusted.
FIG. 13A is a circuit diagram showing the configuration of the two-phase clock signal generation section 104 in the two-phase clock signal generation apparatus 101 shown in FIG. 12, partly shown in block shape. As shown in FIG. 13A, in the two-phase clock signal generation section 104, the machine clock signal MCK output from the machine clock signal output section 102 is converted into a signal IMCK using an inverter gate 108 and the input to one of the input terminals of a first OR gate 109. Furthermore, the machine clock signal MCK is directly input to one of the input terminals of a second OR gate 110.
The output signal (OR1) of the first OR gate 109 is output as the B-phase clock signal via an inverter gate 111. In addition, the B-phase clock signal is converted into a delayed B-phase clock signal (B-d) that is delayed using a second delay control section (delay circuit section) 112b and input to the other input terminal of the second OR gate 110. On the other hand, the output signal (OR2) of the second OR gate 110 is output as the A-phase clock signal via an inverter gate 113. Furthermore, the A-phase clock signal is converted into a delayed A-phase clock signal (A-d) that is delayed using a first delay control section (delay circuit section) 112a and input to the other input terminal of the first OR gate 109.
FIG. 13B is a circuit diagram showing the configuration of the first delay control section 112a, partly shown in block shape. Since the first delay control section 112a and the second delay control section 112b have the same configuration, the configuration of the first delay control section 112a is described below.
In the first delay control section 112a, multi-stage delay buffers 114, each stage formed of two inverter gates 114a and 114b connected in series, are connected in series. In the first delay control section 112a, the propagation delay time in one single delay buffer 114 is used as one unit of the delay time for adjustment. Furthermore, a switch 115 is provided between the input terminal of the first-stage delay buffer 114 and the output terminal of the first delay control section 112a. Moreover, one switch 115 is provided between the output terminal of each of the delay buffers 114 and the output terminal of the first delay control section 112a. The ON/OFF operation of each of the switches 115 is controlled by the output signal of a decoder 116. The decoder 116 decodes the setting data output from the control circuit section 103 and outputs a control signal for turning ON one of the switches 115. As described above, the two-phase clock signal generation section 104 controls the delay values of the first and second delay control sections 112a and 112b on the basis of the setting data output from the control circuit section 103, thereby adjusting the non-overlap time between the A-phase clock signal and the B-phase clock signal.
As described above, in the conventional non-overlap clock signal generator, delay fluctuation amounts due to temperature fluctuations and power supply voltage fluctuations are stored in memory beforehand, and the delay values of the delay control sections are controlled on the basis of the data to adjust the non-overlap time. Hence, in the conventional non-overlap clock signal generator, individual differences in components due to fluctuations during production, etc. cannot be optimized. In particular, a circuit requiring higher speed clock signals is required to be designed so that the non-overlap time thereof has a sufficient margin. Therefore, the design is required to be performed on the assumption that fluctuations occur such that the non-overlap time becomes maximum, that is, the H-level zones of the non-overlap clock signals become minimum. As a result, the conventional non-overlap clock signal generator leads to increase in circuit power consumption. Furthermore, a large-scale system containing a temperature sensor, a power supply voltage sensor, a CPU, etc. is required to be constructed, whereby there is a problem of causing increase in circuit size.